1. Field of the Invention
The present invention relates to an inter-processor communication technology under a multiprocessor environment.
2. Description of the Related Art
There is a communication offload technology for executing communication processing by a main processor and another processor to advance high-speed communication processing and load reduction. In such a multiprocessor processing, a shared memory is arranged between the processors and communication is performed between the processors via the shared memory.
For example, a shared memory is arranged between a main system on the main processor side, in which an application is operated, and a subsystem on the communication offload processor side. The main processor writes transfer data into the shared memory and delivers address information in a memory area, where the transfer data is written, to the communication offload processor by inter-processor communication. The communication offload processor reads the transfer data using the delivered address information and executes sending and receiving processing to an external device.
When the multiprocessing system executes data transfer between the processors via the shared memory, the system is required to suitably process data cached in a cache memory included in each processor. If the system does not suitably process to write the data cached in the cache memory into the shared memory, there is a possibility that the data in the shared memory is overwritten, so that the system cannot be normally operated.
For example, a cache memory having a configuration having a plurality of cache lines having a fixed length (e.g., 32-byte length) is considered. In such a cache memory, when data cached in the cache memory of each processor is written into a shared memory, a system needs to perform control so that other data does not exist on the cache lines to be written. This is because a cache writing operation is performed per cache line. If this restriction is not protected, the cache writing operation overwrites the other data area existing on the same cache line. In order to prevent this overwriting, it is necessary that an application prepares data in which a transfer data writing area in a shared memory is aligned with a cache line in a cache memory or processes to copy the data to an aligned area. Such processing becomes complicated. Further, a conventionally used application not having such processing is inapplicable for a multiprocessor environment as it is.
Further, when the system transfers data between processors via a shared memory, it can be also considered that a cache function is made to be turned off.
However, when the cache function is made to be completely turned off, the performance of the system decreases and communication throughput decreases greatly.
Japanese Patent Application Laid-Open No. 8-305633 and U.S. Pat. No. 6,466,988 (Japanese Patent Application Laid-Open No. 2000-194680) discuss a data transfer system using a shared memory under a multiprocessor environment.
The system discussed in Japanese Patent Application Laid-Open No. 8-305633 performs an operation for invalidating data corresponding to a reference area cached in a cache memory included in a self-processor when the system refers to a data area belonging to another processor. The system discussed in U.S. Pat. No. 6,466,988 (Japanese Patent Application Laid-Open No. 2000-194680) automatically synchronizes content of a cache memory included in each processor by including a coherence function in a cache memory on the system.
As for aforementioned description, complicated processing is necessary for preventing overwriting data in a shared memory. Further, there is a possibility that a conventionally used application that is not a multiprocessor system is inapplicable to the multiprocessor environment as it is.
Furthermore, a method not using a cache function reduces the performance of a system.